1. Field of the Invention
The present invention relates to a motion picture motion compensating frame-to-frame predictive coding device and, more particularly, to a motion vector detection circuit capable of executing motion vector search processing at a high speed.
2. Description of the Related Art
In conventional motion picture coding devices employing a motion picture motion compensating frame-to-frame predictive coding system whose representative is MPEG or H.261, a frame picture to be coded is divided into small regions of 16 pixels by 16 lines called macro blocks and for each macro block, the frame picture is compared with an immediately preceding (or immediately succeeding) frame picture which is locally decoded to determine to which part of the immediately preceding (or succeeding) frame picture each macro block corresponds. The above-described series of processing is called motion vector search and enables drastic compression of the volume of encoding by executing motion compensation based on obtained motion vectors.
On the other hand, the biggest problem with real-time operation of such a motional picture coding device is how much a processing time of this motion vector search can be reduced. More specifically, a common method of obtaining a motion vector is, assuming that fixed bounds in the horizontal direction and the vertical direction with respect to the position of a macro block to be coded is a search range, matching each pixel (256 pixels in MPEG2/H.261) within the macro block with a block of the same size within the search range to obtain a region having a minimum value, and defining a difference in a position in space between the region and the macro block as a motion vector.
For strictly searching a motion vector here, it is necessary to conduct matching while shifting the macro block one pixel by one pixel to every nook and corner in the search range. As the search range is enlarged, enormous volume of computation will be required.
As an example, in a case where a search range with a width from xe2x88x9215 pixels to +15 pixels in both the horizontal and vertical directions with respect to a macro block is searched using a microprocessor, the volume of arithmetic required for one trial includes 256 times of memory accesses, 256 times of subtractions, 256 times of turning the results into absolute values, 256 times of addition of the results of the absolute values and one time of comparison with a former addition result, 961 (31xc3x9731) times of repetition of which arithmetic determines one motion vector.
Therefore, a motion picture coding device which executes real-time processing ordinarily requires hardware dedicated to motion vector search. Calculation of a sum of difference absolute values between 256 pixels, for example, may be realized by processing by 256 parallel arithmetic units.
The problem in this case, however, is the number of times of data reading from a frame memory for parallel arithmetic. More specifically, since 256 times of memory accesses is executed per one trial, 246,016 (256xc3x97961) times of memory accesses will be required for all the trials per one motion vector, which is a bottleneck in dedicated hardware.
As described in the foregoing, for realizing real-time processing, conventional motion vector detection circuits should adopt an expensive high-speed memory, reduce a motion vector search range or use a plurality of motion vector detection circuits in parallel.
A first object of the present invention is to provide a motion vector detection circuit, intended to solve the above-described problems, which is capable of conducting high-speed coding of a motion picture by executing motion vector search at a high speed.
A second object of the present invention is to provide a motion vector detection circuit allowing a sequencer of a control means (controller) to be simply structured and a motion vector search range to be changed with ease.
A third object of the present invention is to provide a motion vector detection circuit enabling reduction of a circuit scale while reducing the number of times of data reading from a frame memory.
According to one aspect of the invention, a motion vector detection circuit for conducting motion vector search by, with a frame picture as a coding target being divided into a plurality of macro blocks of m pixels by n lines, comparing a plurality of comparison target blocks of m pixels by n lines within a search range of a predetermined size set in a frame picture immediately preceding or succeeding in time the frame picture and the macro block as the current coding target to specify a comparison target block most similar to the macro block as the current coding target, comprises
first storage means for storing each pixel data of the macro block as the current coding target,
second storage means of m by n matrix arrangement having two-dimensional or one-dimensional structure for storing each pixel data of the comparison target block,
arithmetic means for performing parallel arithmetic of an absolute value of a difference between the corresponding pixels in the comparison target block stored in the second storage means and in the macro block stored in the first storage means to calculate a sum of the respective difference absolute values,
result holding means for holding the sum of difference absolute values, and
control means for updating the result holding means by the sum of difference absolute values from the arithmetic means only when the sum of difference absolute values from the arithmetic means is smaller than a sum of difference absolute values held in the result holding means and causing the second storage means to store each pixel data of other the comparison target block which comes next at a position shifted by one pixel or one line within the search range.
In the preferred construction, the second storage means is composed of a number mxc3x97n of registers which have two-dimensional structure where inputs and outputs of laterally adjacent registers are bidirectionally connected and inputs and outputs of vertically adjacent registers are unidirectionally connected.
In another preferred construction, the second storage means is composed of a number mxc3x97n of registers which have two-dimensional structure where inputs and outputs of laterally adjacent registers are bidirectionally connected and inputs and outputs of vertically adjacent registers are unidirectionally connected, and the register is composed of a flip-flop and a four-input one-output selector.
In another preferred construction, the second storage means is composed of a number mxc3x97n of registers which have one-dimensional structure where inputs and outputs of laterally adjacent registers are unidirectionally connected.
In another preferred construction, the second storage means is composed of a number mxc3x97n of registers which have one-dimensional structure where inputs and outputs of laterally adjacent registers are unidirectionally connected, and the register is composed of a flip-flop and a two-input one-output selector.
In another preferred construction, the control means, at the time of updating the result holding means by the sum of difference absolute values from the arithmetic means, stores reference position data of the comparison target block corresponding to the sum of difference absolute values.
In another preferred construction, the arithmetic means comprises subtraction means for performing subtraction between the corresponding pixels in the comparison target block and the macro block, absolute value arithmetic means for turning the result of subtraction between the pixels into an absolute value to obtain the difference absolute value, and addition means for adding the difference absolute values to calculate the sum of difference absolute values.
In another preferred construction, the motion vector detection circuit further comprises comparison means for comparing the sum of difference absolute values from the arithmetic means and a sum of difference absolute values held in the result holding means, wherein
the control means updates the result holding means by the sum of difference absolute values from the arithmetic means only when the sum of difference absolute values from the arithmetic means is smaller than a sum of difference absolute values held in the result holding means based on a comparison result from the comparison means.
According to another aspect of the invention, a motion vector detection circuit for conducting motion vector search by, with a frame picture as a coding target being divided into a plurality of macro blocks of m pixels by n lines, comparing a plurality of comparison target blocks of m pixels by n lines within a search range of a predetermined size set in a frame picture immediately preceding or succeeding in time the frame picture and the macro block as the current coding target to specify a comparison target block most similar to the macro block as the current coding target, comprises
first storage means for storing each pixel data of the macro block as the current coding target,
second storage means of m by n matrix arrangement having two-dimensional or one-dimensional structure for storing each pixel data of the comparison target block, and
control means for conducting comparison processing of the comparison target block stored in the second storage means and the macro block stored in the first storage means while sequentially storing, in the second storage means, each pixel data of other the comparison target block which comes next at a position shifted by one pixel or one line within the search range.
In the preferred construction, the second storage means is composed of a number mxc3x97n of registers which have two-dimensional structure where inputs and outputs of laterally adjacent registers are bidirectionally connected and inputs and outputs of vertically adjacent registers are unidirectionally connected.
In another preferred construction, the second storage means is composed of a number mxc3x97n of registers which have one-dimensional structure where inputs and outputs of laterally adjacent registers are unidirectionally connected.
In another preferred construction, the motion vector detection circuit further comprises arithmetic means for performing parallel arithmetic of an absolute value of a difference between the corresponding pixels in the comparison target block stored in the second storage means and in the macro block stored in the first storage means to calculate a sum of the respective difference absolute values, and result holding means for holding the sum of difference absolute values, wherein
the control means updates the result holding means by the sum of difference absolute values from the arithmetic means only when the sum of difference absolute values from the arithmetic means is smaller than a sum of difference absolute values held in the result holding means.
Other objects, features and advantages of the present invention will become clear from the detailed description given herebelow.